الدرس العاشر – بناء معالج بسيط – 16 بت (3)

سلسلة من الدروس في لغة توصيف العتاد الصلبVHDL

الدرس العاشر – بناء معالج بسيط – 16 بت (3)

وحدة التحكم (تتمة)

لمعرفة إشارات التحكم اللازمة لكل عملية يجب أولاً تحديد عدد المراحل التي تحتاجها كل من العمليات الستة. يتم تحديد عدد المراحل كما وجدنا من خلال عدد مرات استخدام الممر.

–         عمليتي mv , mvi  تستخدمان الممر مرة واحدة و بالتالي مرحلة واحدة.

–         العمليات الحسابية و المنطقية تستخدم الممر 3 مرات لذلك بحاجة إلى 3 مراحل.

يوضح الجدول التالي الإشارات المطلوبة لتنفيذ العمليات في كل المراحل.

T3

T2

T1

Operation

Ryout,Rxin,Done,Clear

mv Rx,Ry

DINout ,Rxin,Done,Clear

mvi Rx,DATA

Gout,Rxin,Done,Clear

Rxout,Op,Gin

Ryout,Ain

add Rx,Ry

Gout,Rxin,Done,Clear

Rxout,Op,Gin

Ryout,Ain

sub Rx,Ry

Gout,Rxin,Done,Clear

Rxout,Op,Gin

Ryout,Ain

and Rx,Ry

Gout,Rxin,Done,Clear

Rxout,Op,Gin

Ryout,Ain

or Rx,Ry

 تشترك جميع العمليات بالفترة الزمنية T0  و التي تعتبر بمثابة تهيئة للانتقال من عملية إلى أخرى يتم خلالها قراءة التعليمة التالية. يوضح الشكل التالي الإشارات في كل المراحل بشكل تفصيلي لجميع العمليات.

Instruction

T_priod IRin Rin Rout Gout DINout Ain Gin ALU0 ALU1 Clear Done
mv T0

1

0

0

0

0

0

0

0

0

0

0

mv T1

0

1

1

0

0

0

0

0

0

1

1

mvi T0

1

0

0

0

0

0

0

0

0

0

0

mvi T1

0

1

0

0

1

0

0

0

0

1

1

add T0

1

0

0

0

0

0

0

0

0

0

0

add T1

0

0

1

0

0

1

0

0

0

0

0

add T2

0

0

1

0

0

0

1

0

0

0

0

add T3

0

1

0

1

0

0

0

0

0

1

1

sub T0

1

0

0

0

0

0

0

0

0

0

0

sub T1

0

0

1

0

0

1

0

0

0

0

0

sub T2

0

0

1

0

0

0

1

0

1

0

0

sub T3

0

1

0

1

0

0

0

0

0

1

1

and T0

1

0

0

0

0

0

0

0

0

0

0

and T1

0

0

1

0

0

1

0

0

0

0

0

and T2

0

0

1

0

0

0

1

1

0

0

0

and T3

0

1

0

1

0

0

0

0

0

1

1

or T0

1

0

0

0

0

0

0

0

0

0

0

or T1

0

0

1

0

0

1

0

0

0

0

0

or T2

0

0

1

0

0

0

1

1

1

0

0

or T3

0

1

0

1

0

0

0

0

0

1

1

LIBRARY ieee;

 USE ieee.std_logic_1164.all;

 ——————————————-

 ENTITY cu IS

 PORT (                   IR: IN STD_LOGIC_VECTOR(8 DOWNTO 0);

                               Tstep: IN STD_LOGIC_VECTOR(1 DOWNTO 0);

                               Run,Reset: IN STD_LOGIC;

                               Rout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

                               Gout,DINout: OUT STD_LOGIC;

                               Rin : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

                               IRin,Ain,Gin,Clear,Done: OUT STD_LOGIC;

                               Op : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));

END cu;

 ——————————————-

 ARCHITECTURE Behavioral OF cu IS

BEGIN

CUsignals:Process(IR,Tstep,Reset,Run)

VARIABLE Xreg:STD_LOGIC_VECTOR(7 DOWNTO 0);

VARIABLE Yreg:STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN

IF(Run =’1′) THEN

IF (Reset = ‘0’) THEN

 Rout <= X”00″; Rin <= X”00″; Gout <= ‘0’; DINout <= ‘0’; IRin <= ‘1’; Ain <= ‘0’;                     Gin <= ‘0’; Clear <= ‘1’; Done <= ‘0’; Op <= “00”;

ELSE

  Clear <= ‘0’;

  CASE IR(5 DOWNTO 3) IS

WHEN “000” => Xreg := “00000001”;

WHEN “001” => Xreg := “00000010”;

WHEN “010” => Xreg := “00000100”;

WHEN “011” => Xreg := “00001000”;

WHEN “100” => Xreg := “00010000”;

WHEN “101” => Xreg := “00100000”;

WHEN “110” => Xreg := “01000000”;

WHEN “111” => Xreg := “10000000”;

WHEN OTHERS =>  Xreg := “ZZZZZZZZ”;

END CASE;

CASE IR(2 DOWNTO 0) IS

WHEN “000” => Yreg := “00000001”;

WHEN “001” => Yreg := “00000010”;

WHEN “010” => Yreg := “00000100”;

WHEN “011” => Yreg := “00001000”;

WHEN “100” => Yreg := “00010000”;

WHEN “101” => Yreg := “00100000”;

WHEN “110” => Yreg := “01000000”;

WHEN “111” => Yreg := “10000000”;

WHEN OTHERS =>  Yreg := “ZZZZZZZZ”;

END CASE;

CASE Tstep IS

WHEN “00” => — T0

                IRin <= ‘1’; Done <= ‘0’; Rin <= X”00″; Rout <= X”00″;

WHEN “01” => — T1

                CASE IR(8 DOWNTO 6) IS

                WHEN “000” => — move instruction

            IRin <= ‘0’; Rout <= Yreg; Rin <= Xreg;  Gout <= ‘0’; DINout <= ‘0’; Clear <= ‘1’; Done <= ‘1’;

                WHEN “001” => — move immadiate instruction

 IRin <= ‘0’; Rout <= “00000000”; Rin <= Xreg; Gout <= ‘0’; DINout <= ‘1’; Clear <= ‘1’; Done <= ‘1’;

              WHEN “010” => –Add instruction

  IRin <= ‘0’; Rout <= Yreg; Gout <= ‘0’; DINout <= ‘0’; Rin <= “00000000”; Ain <= ‘1’;

                WHEN “011” => –Sub instruction

  IRin <= ‘0’; Rout <= Yreg; Gout <= ‘0’; DINout <= ‘0’; Rin <= “00000000”; Ain <= ‘1’;

                WHEN “100” => –AND instruction

  IRin <= ‘0’; Rout <= Yreg; Gout <= ‘0’; DINout <= ‘0’; Rin <= “00000000”; Ain <= ‘1’;

                WHEN “101” => –OR instruction

  IRin <= ‘0’; Rout <= Yreg; Gout <= ‘0’; DINout <= ‘0’; Rin <= “00000000”; Ain <= ‘1’;

                WHEN OTHERS => –for future work but we’ll consider it as AND

 IRin <= ‘0’; Rout <= Yreg; Gout <= ‘0’; DINout <= ‘0’; Rin <= “00000000”; Ain <= ‘1’;

                END CASE;

WHEN “10” => — T2

         CASE IR(8 DOWNTO 6) IS

         WHEN “000” => — move instruction

                 Clear <= ‘1’;

          WHEN “001” => — move immadiate instruction

                  Clear <= ‘1’;

           WHEN “010” => –Add instruction

           Ain <= ‘0’; Rout <= Xreg; Gout <= ‘0’; DINout <= ‘0’; Gin <= ‘1’; Op <= “00”;

            WHEN “011” => –Sub instruction

            Ain <= ‘0’; Rout <= Xreg; Gout <= ‘0’; DINout <= ‘0’; Gin <= ‘1’; Op <= “01”;

            WHEN “100” => –AND instruction

            Ain <= ‘0’; Rout <= Xreg; Gout <= ‘0’; DINout <= ‘0’; Gin <= ‘1’; Op <= “10”;

             WHEN “101” => –OR instruction

              Ain <= ‘0’; Rout <= Xreg; Gout <= ‘0’; DINout <= ‘0’; Gin <= ‘1’; Op <= “11”;

              WHEN OTHERS => –for future work but we’ll consider it as AND

              Ain <= ‘0’; Rout <= Xreg; Gout <= ‘0’; DINout <= ‘0’; Gin <= ‘1’; Op <= “10”;

               END CASE;

WHEN “11” => — T3

                CASE IR(8 DOWNTO 6) IS

                 WHEN “000” => — move instruction

                              Clear <= ‘1’;

                   WHEN “001” => — move immadiate instruction

                               Clear <= ‘1’;

                    WHEN “010” => –Add instruction

Gin <= ‘0’; Rin <= Xreg; Rout <= “00000000”; Gout <= ‘1’; DINout <= ‘0’; Clear <= ‘1’; Done <= ‘1’;

                     WHEN “011” => –Sub instruction

Gin <= ‘0’; Rin <= Xreg; Rout <= “00000000”; Gout <= ‘1’; DINout <= ‘0’; Clear <= ‘1’; Done <= ‘1’;

                      WHEN “100” => –AND instruction

 Gin <= ‘0’; Rin <= Xreg; Rout <= “00000000”; Gout <= ‘1’; DINout <= ‘0’; Clear <= ‘1’; Done <= ‘1’;

                      WHEN “101” => –OR instruction

 Gin <= ‘0’; Rin <= Xreg; Rout <= “00000000”; Gout <= ‘1’; DINout <= ‘0’; Clear <= ‘1’; Done <= ‘1’;

                      WHEN OTHERS => –for future work but we’ll consider it as AND

Gin <= ‘0’; Rin <= Xreg; Rout <= “00000000”; Gout <= ‘1’; DINout <= ‘0’; Clear <= ‘1’; Done <= ‘1’;

                       END CASE;

WHEN OTHERS => Clear <= ‘1’;

END CASE;

END IF;

END IF;

END Process;

END Behavioral;

About زين العابدين

مهندس حواسيب - معهد IDA - جامعة Braunshweig التقنية.
هذا المنشور نشر في دروس تعليمية وكلماته الدلالية , , , . حفظ الرابط الثابت.

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